A 39.4-mW 300 MHz-BW 70.9 dB-SNDR Hybrid ADC With Resistive Input and 200 fs, rms-Jitter Tolerance

This paper presents a power-efficient hybrid ADC architecture: a low-resolution CT Delta-Sigma modulator (DSM) followed by a time-interleaved pipeline stage which further quantizes the quantization noise of the DSM. In the frontend CT DSM, the resistive input makes the ADC easy-to-drive, and the direct-charge-dump feedback provides a high jitter-immunity; the quantization of the backend is mainly performed by SAR ADCs, providing a high power efficiency. Capacitor flipping is proposed in the frontend to implement an intrinsically linear 1.5b direct-charge-dump feedback. Nested time-interleaving is proposed in the backend in order to assign the major quantization work to SAR ADCs. Primary-secondary sampling with improved timing is utilized to eliminate timing skew issue while gain more available sampling time and relax backend noise requirement. The ADC is fabricated in 28nm CMOS process and achieves 70.9dB SNDR in 300MHz BW with 39.4mW power consumption, yielding 169.7dB Schreier FoM, and the band-edge performance is preserved up to 200fs,rms clock jitter.