A 7-Level 18-Wire-State Trio-Signaling Transmitter for MIPI C-PHY 3.0 Interfaces

This paper presents a MIPI C-PHY v3.0 TX, which adopts trio-signaling using three wires per lane. Each line supports 7-level signaling, enabling 18 wire states to map 32-bit data into 9 symbols, achieving 3.56 bits/symbol efficiency. Balanced coding maintains constant driver current, enhancing SSO noise immunity, and embedded clocking is achieved by prohibiting identical consecutive wire states, eliminating the need for a separate clock channel. Although 7 levels are used, only four detection regions are needed due to restricted level combinations. Fabricated in 28-nm CMOS, the TX achieves 17.78 Gbps at 5 GSps with a 3.10 pJ/bit FoM and occupies 0.0757 mm².