A 256-Element Slepian Beamforming Accelerator With Analog Compute-In-Memory Multiplication and Accumulation

IEEE Solid-State Circuits Letters 2026

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Authors: Wei‐Chun Wang, Shida Zhang, Coleman DeLude, Laith A. Shamieh, Nael Mizanur Rahman, Isha Chakraborty, Justin Romberg, Saibal Mukhopadhyay
DOI: 10.1109/lssc.2026.3690381
Cited by: 1
References: 10

Abstract

An analog compute-in-memory Slepian beamforming accelerator is introduced for large-scale MIMO. The design performs complex-valued vector–matrix multiplication in the analog domain to project 256 I/Q inputs into a low-dimensional Slepian subspace and uses a digital backend with 4-tap FIR filters to generate one output beam. A test chip fabricated in 28 nm CMOS demonstrates a 20.5 dB peak-to-sidelobe ratio over a 280 MHz bandwidth while consuming 414 mW.

Fields of Study & Subjects

Radio Frequency Integrated Circuit Design Advanced Power Amplifier Design Advancements in PLL and VCO Technologies

Publication details

Journal / source
IEEE Solid-State Circuits Letters
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Volume
9
Pages
154–157
Publication date
1 January 2026