Design and Implementation of a 256-Point FFT Hardware for Power Spectral Density Computation in EEG-Based Mental Stress Recognition

This paper presents a high-throughput, low-latency 256-point Fast Fourier Transform (FFT) architecture employing two radix-16 butterfly ($\text{BS}_{16}$) units with a conflict-free dataflow structure and an integrated multiplierless power-accumulation (pAD) module for area-efficient power spectral density (PSD) computation. The design is synthesized using Synopsys Design Compiler in UMC 40-nm CMOS technology, achieving an area of$0.429 \text{mm}^{2}$for the standalone FFT and$0.477 \text{mm}^{2}$when combined with the pAD unit. The architecture delivers a latency of 62 clock cycles and a throughput of$3.2 \text{GS} / \mathrm{s}$, with a measured power consumption of 30.96 mW. The proposed design provides accurate PSD estimation, further validated through downstream electroencephalography (EEG) based, machine-learning-driven mental stress recognition. The 256-point FFT block achieves a mean Peak Signal-to-Noise-Ratio (PSNR) of 47.42 dB and a mean correlation coefficient of 0.998, while the hardwaresynthesized PSD achieves a mean Spectral Distortion Measure (SDM) of$56.98 \text{dB}^{2}$and Spectral SNR (SSNR) of 48.72 dB. Subsequently, several discriminative features are extracted from the estimated PSD and are used to train benchmark machine learning classifiers implemented in Python. Among them, XGBoost attains the best overall performance with an accuracy of 89.01%, alongside strong precision$(88.21 \%)$, recall$(88.76 \%)$, and F1 Score$(88.48 \%)$, confirming its suitability for portable, real-time EEG-based stress recognition applications.