Non-Iterative Square-Wave Modeling of Multistage CMOS Dickson Rectifiers for RF Energy Harvesting

Performance evaluation of UHF RF energy harvesters is limited by the complexity of analyzing rectifiers under sinusoidal excitation. This work presents a non-iterative square-wave-based analytical method for modeling multistage CMOS Dickson rectifiers. Closed-form expressions for output voltage, output power, and power conversion efficiency (PCE) are derived using a fixed-amplitude scaling factor (K= π/4). The approach is validated through post-layout simulations and measurements in 65-nm CMOS at 2.4 GHz. Simulated and modeled output power deviations are 2.19%, 2.09%, and 2.67% for single-, three-, and six-stage rectifiers, respectively, with output voltage and PCE deviations below 3.10% across input power and load conditions. The model is further evaluated from 0.5 to 3 GHz and across process corners. A fabricated three-stage prototype (86 μm × 60 μm) achieves a peak PCE of 57.94%, a power dynamic range (PDR) of 22 dB, and a sensitivity of −23.5 dBm atVOUT= 1 V. Measured results show deviations of 2.85% in PCE and 2.74% in output power from simulation, confirming the accuracy of the proposed square-wave analytical model.