An Input-Driving-Relaxed Noise-Shaping SAR ADC With Amplifier-Reused In-Loop Buffering and NTF Leakage Reshaping

This paper presents a third-order noise-shaping successive approximation register (NS SAR) analog-to-digital converter (ADC) with embedded input buffering capability and a PVT robust error-feedback (EF)-based filter. An Amplifier-Reused In-Loop Buffering (AILB) architecture is proposed to serve multiple purposes: first, it reuses the residue amplifier for input driving, obviating the need for an explicit buffer and its related noise penalty. Second, it inherently suppresses the sampling kT/C noise without explicit noise-cancelling operations. Lastly, it facilitates a simpler bias design compared to using explicit buffers. To enable a PVT-robust EF noise filter, a noise transfer function (NTF) leakage reshaping (NLRS) technique is proposed, allowing the NTF leakage component to be shaped to the first order. Prototyped in 65 nm CMOS technology, this design achieves 82.0 dB signal-to-noise-distortion ratio (SNDR) with 500 kHz bandwidth (BW) under an oversampling ratio (OSR) of 8. The prototype’s total power consumption is 126.8 μW (including the input driving buffer), achieving a Schreier figure-of-merit (FoM) of 178.0 dB.