Approaches for Reducing Power Consumption of 200-GHz Passive-Mixer First BiCMOS Receivers

This paper reports approaches for reducing the power consumption for a passive switching mixer first receiver that are demonstrated in a 200-GHz low-IF (3.75 GHz) BiCMOS receiver prototype. The receiver employs a 2ndorder sub-harmonic mixer that allows the use of a 100-GHz LO signal generated by HBT's to reduce DC power consumption. Additionally, the receiver employs a single mixer instead of I/Q down converter to further lower DC power consumption by reducing the number of LO chains and eliminating the need for the generation of I/Q LO signals. The receiver fabricated in a GF BiCMOS process with 45-nm CMOS and HBT fT/fmaxof 410/610 GHz exhibits a 16-GHz bandwidth, a single side band noise figure of 23 dB, OPldB of 0.5 dBm and an out-of-band gain roll-off of ~10 dB over 15 GHz at RF while consuming 96 mW not including that for an ADC.