SAPH-Kyber: Stage-Aware Pipeline Hardening for CRYSTALS-Kyber NTT Against Transient Faults

As lattice-based cryptography transitions into global standards, the physical security of hardware implementations like CRYSTALS-Kyber against side-channel vulnerabilities has become a critical research priority. This paper presents a comprehensive temporal sensitivity analysis of a Kyber Number Theoretic Transform (NTT) hardware core under transient fault conditions. Utilizing a custom-built Verilog simulation framework, we perform an automated sensitivity sweep by injecting single-cycle glitches into the arithmetic pipeline across all seven NTT stages. Our results reveal a significant Error Diffusion Gradient: faults in the initial pipeline stages ($0-2$) result in global polynomial corruption, affecting all 256 coefficients, whereas latestage faults remain localized to as few as two coefficients. We characterize the predictable mathematical leakage resulting from these faults (e.g., error magnitudes of 34 and 67) and demonstrate their exploitability for secret key recovery via Differential Fault Analysis (DFA). Based on these findings, we propose a Selective Pipeline Hardening strategy that concentrates hardware protection such as parity-based error detection on high-diffusion temporal windows (Stages 0-3). This targeted approach provides robust security with a significant reduction in area and power overhead compared to traditional full-core redundancy, offering a scalable methodology for securing post-quantum processors in resource-constrained FPGA and ASIC environments.