Life Cycle Assessment of 3D Stacked Multi-Chip Assemblies: Comparison of Three Multi-Layer CMOS Image Sensors

To prevent the growth of information and communication technologies impacts, environmental impact assessments should be systematized using the life cycle assessment (LCA) method when developing new computing devices. However, this is difficult to implement due to challenges related to the life cycle inventory, lack of adequate tooling and lack of data. This is particularly true for complex devices such as multichip assemblies. This paper introduces a novel parametric LCA model for 3D stacked multi-chip assemblies which only requires a limited set of design parameters. Using this LCA model, we present the first comparative LCA of three multi-layer CMOS Image Sensors (CIS) from the literature. Our results show that the environmental impacts of multi-layer CIS are primarily driven by the silicon wafer manufacturing. The most powerefficient CIS can only offset its greater fabrication impacts after a long utilization period. Our results also demonstrate that stacking a third layer of silicon can reduce manufacturing impacts by reducing silicon die sizes. The proposed LCA model and environmental data are released as open source to facilitate future LCA works on digital devices.