Wafer-Scale Fabrication and Spatial Uniformity Evaluation of SQUIDs With Submicron Josephson Junctions

This paper reports the wafer-scale fabrication of dc superconducting quantum interference devices (dc-SQUIDs) on 4-inch silicon wafers, employing a sub-micron Josephson junction cross-line process that integrates i-line stepper lithography, in-situ trilayer deposition, and a self-aligned insulating layer. Using a stratified regional sampling strategy, 10 SQUIDs are selected from each of the center, transition, and edge regions of the wafer (achieving a total coverage of 49.2%), and the spatial uniformity of key parameters such as critical current, voltage swing, and system flux noise is systematically evaluated. The test results show that the critical currents for the central, transition, and edge regions are (25.4±1.77) μA, (22.4±2.13) μA, and (16.2±2.81) μA, respectively; their corresponding voltage swings are (275±5.95) μV, (255±17.8) μV, and (146±44.7) μV, respectively; and the system flux noises are (1.74±0.131) μΦ0/√Hz, (1.97±0.0880) μΦ0/√Hz, and (2.70±0.452) μΦ0/√Hz, respectively. Statistical analysis shows that from the center to the edge, the critical current and voltage swing demonstrate a downward trend, while the system flux noise shows a trend of deterioration. The standard deviation of these parameters gradually increases from the center to the edge, which indicates poorer parameter consistency and more pronounced fluctuations in the region. Further analysis of the coefficient of variation (CV) shows that the CVs of key parameters in the central and transition regions are all below 10%. This verifies that the process route, particularly in these central and transition regions, possesses excellent spatial uniformity, providing a crucial process foundation and data support for the large-scale manufacturing of high-performance SQUIDs.