AC Power Delivery for Fast Phase Logic

Biasing remains one of the key scalability bottle necks in superconducting digital circuits, as traditional DC bias networks impose excessive power dissipation, large direct current requirements resulting in significant power overhead. Fast Phase Logic (FPL), an all-Josephson Junction (JJ) logic family, achieves ultra-high density by eliminating resistors and large inductors; however, existing FPL designs still rely on DC bias. This paper introduces a novel architecture: AC-biased FPL (ACFPL), which integrates single-phase AC/SFQ converters with FPL cells to deliver bias currents as quantized pulses, thereby eliminating the need for a global DC distribution network. Circuit-level simulations at 10 GHz demonstrate that AC biasing achieves up to 25× lower power consumption compared to DC bias for RSFQ circuits, and 14.3× reduction in power consumption for FPL circuits in our design-under-test (DUT), which combines FPL JTL, FPL DFF, and FPL AND cells. These results estab lish ACFPL as a scalable and energy-efficient alternative for large-scale superconducting digital systems, effectively combining compact FPL cell design with practical AC/SFQ bias delivery, allowing superconductor VLSI.