Design Automation Systems for Rapid Single Flux Quantum Logic

We present JSIC(Josephson-junction-based Superconductor Integrated Circuits)-EDA, a specialized EDA suite for superconducting digital integrated circuits, developed based on validated cell libraries of different processes including SIMIT-Nb03, SIMIT-Nb03P, and SIMIT-Nb04. The system integrates 3D superconductor process models, digital PDKs, and advanced timing, logic, and physical models, enabling full automation for digital design on these processes. JSIC-EDA supports seamless tool integration and automated workflow scheduling. The JSICcompiler platform provides an RTL-to GDSII synthesis flow for RSFQ circuits, featuring logic synthesis, placement, clock tree synthesis, and JTL/PTL routing for 3D processes. A developer tool, JSIClibrary, is built upon this foundation to facilitate custom cell library design. JSICsim supports RCSJ and RCLSJ junction models with large-scale parallel simulation, serving as the analog engine for tools like JSICpower, which performs power grid modeling, dynamic current analysis, and magnetic/flux analysis. JSICtime offers static, dynamic, and Monte-Carlo timing analysis for RSFQ logic, supporting both design verification and post-fabrication testing. JSICvision enables automated testing and response analysis, validated on fabricated superconducting chips. Built on a scalable framework, JSIC-EDA is actively expanding with new algorithmic modules to advance automation in superconducting IC design, analysis, and testing.