Hardware-Efficient Taylor Series-Based Optimal Unsigned Square Rooter for Fast and Low Power Computation

Approximate computing is a rising technique aimed at developing arithmetic circuits that minimize power usage, resource consumption, and latency for error-tolerant applications, enabling faster and more efficient circuits suitable for resource-constrained environments. Square root computation is vital in hardware design for image and signal processing, but it’s resource-intensive and power-hungry. Optimizing it can boost power efficiency and performance. This work presents a hardware-efficient, fast and low-power Taylor series-based optimal unsigned square rooter (TSOSQR) designed for approximate square root computation of a 2n-bit unsigned integer using addition and shift operations. Compared to a precise restoring array-based square rooter architecture, the suggested square rooter design uses 79% fewer resources, operates 56% faster, and provides a 81% increase in power savings. These designs are implemented on an Artix-7 FPGA using Verilog-HDL, verified through Xilinx Vivado simulation, and additionally synthesized at the ASIC level using the Cadence Genus Compiler targeting a standard-cell 45nm CMOS technology node. Extensive simulations and a detailed comparison of the proposed design against state-of-the-art approaches show that the TSOSQR effectively balances accuracy and hardware efficiency, significantly reducing power consumption and latency. The paper demonstrates the superior performance of the proposed square rooter in Sobel edge detection, image contrast enhancement, and K-means clustering, with an IoT-enabled FPGA edge vision node design flow, highlighting its effectiveness and advantage over existing approximate designs.