Machine Learning-Based Timing and Power Models for Multiple-Input Switching and Glitch Effects

With continuous technology scaling, accurate and efficient Multiple Input Switching (MIS) modeling is essential for designing high-performance, low-power, and reliable integrated circuits. MIS commonly induces speed-up or slow-down effects on gate timing and may even generate spurious glitches at the outputs, potentially impacting timing, power consumption, and overall circuit reliability. In this article, we propose a unified MIS modeling approach based on Machine Learning (ML), employing efficient and compact Artificial Neural Networks (ANNs) to estimate the timing and power characteristics of MIS-induced transitions and glitches. To achieve this, we evaluate various ML engines and explore different ANN hyperparameters and architectures. Moreover, we introduce an iterative workflow that seamlessly integrates our ANNs into standard cell libraries, striking an optimal balance between model accuracy and size. The proposed framework employs efficient techniques to reduce characterization effort, minimize library size, and improve model accuracy. Experimental evaluation on gates implemented in 7nm FinFET and 45nm bulk CMOS technologies indicates that our models exhibit a strong correlation with SPICE, achieving a meanR2score of 0.997 across all gates and process, voltage, and temperature corners while maintaining low memory demands. Thus, our approach can effectively improve gate-level timing, power, and reliability analysis and guide glitch reduction techniques.