FETTA: Flexible and Efficient Hardware Accelerator for Tensorized Neural Network Training

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Authors: Jinming Lu, Jiayi Tian, Hai Li, Ian A. Young, Zheng Zhang
Cited by: 0
References: 59

Abstract

The increasing demand for on-device training of deep neural networks (DNNs) aims to leverage personal data for high-performance applications while addressing privacy concerns and reducing communication latency. However, resource-constrained platforms face significant challenges due to the intensive computational and memory demands of DNN training. Tensor decomposition emerges as a promising approach to compress model size without sacrificing accuracy. Nevertheless, training tensorized neural networks (TNNs) incurs non-trivial overhead and severe performance degradation on conventional accelerators due to complex tensor shaping requirements. To address these challenges, we propose FETTA, an algorithm and hardware co-optimization framework for efficient TNN training. On the algorithm side, we develop a contraction sequence search engine (CSSE) to identify the optimal contraction sequence with the minimal computational overhead. On the hardware side, FETTA features a flexible and efficient architecture equipped with a reconfigurable contraction engine (CE) array to support diverse dataflows. Furthermore, butterfly-based distribution and reduction networks are implemented to perform flexible tensor shaping operations during computation. Evaluation results demonstrate that FETTA achieves reductions of 20.5×/100.9×, 567.5×/45.03×, and 11609.7×/4544.8× in terms of processing latency, energy, and energy-delay product (EDP) over GPU and TPU, respectively. Moreover, working on the tensorized training, FETTA outperforms prior accelerators with a speedup of 3.87 ∼ 14.63×, and an energy efficiency improvement of 1.41 ∼ 2.73× on average.

Fields of Study & Subjects

Advanced Neural Network Applications Advanced Memory and Neural Computing Neural Networks and Reservoir Computing

Publication details

Journal / source
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Volume
45
Issue
9
Pages
4422–4435
Publication date
12 January 2026
Language
EN