Auto-Mult: A Self-Optimizing Integer Multiplier via Hybrid Decomposition and Automated Parameter Search
Abstract
Integer multipliers serve as fundamental and widely used components that are essential to cryptographic operations. However, designing a general-purpose multiplier remains a significant challenge due to limitations in bitwidth adaptability and hardware efficiency. To address this, we propose Auto-Mult, a self-optimizing integer multiplier via hybrid decomposition strategy. By dynamically combining Karatsuba, Toom-Cook, and Schoolbook algorithms, Auto-Mult achieves bitwidth-adaptive hardware optimization. The key innovation lies in an automated parameter search model based on simulated annealing, which explores the optimal decomposition configuration for any given hardware platform to minimize the area–time product (ATP). FPGA-based experiments show that Auto-Mult achieves up to a 40× improvement in ATP.
Fields of Study & Subjects
Cryptographic Implementations and Security
Numerical Methods and Algorithms
Cryptography and Residue Arithmetic
Publication details
- Journal / source
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Volume
- 45
- Issue
- 9
- Pages
- 4311–4315
- Publication date
- 12 January 2026