Cyclic Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros

Gain-Cell embedded DRAM (GC-eDRAM) is a dense, low power option for embedded memory implementation; however, it suffers from limited data retention time, and therefore, requires periodic refresh operations. This limitation restricts its usage to applications that can tolerate temporary memory blockages. In this work, we propose a cyclic refresh algorithm for GC-eDRAM to ensure 100% memory availability for the user under any user access pattern. A hardware controller that integrates the proposed refresh algorithm was developed, synthesized, and evaluated within a System Verilog simulation framework, demonstrating its functionality, silicon area footprint, and power consumption across diverse workloads and access patterns. The area overhead of the proposed algorithm was significantly smaller than that of state-of-the-art solutions, allowing for a reduced silicon footprint even for relatively small macro sizes, achieving as much as a 40% area reduction compared to standard 6T SRAM solutions. By using this algorithm, GC-eDRAM can be a drop-in replacement for SRAM, providing a high density, low power embedded memory solution.