High-Speed Redundancy Analysis for Complex Spare Structures

Techniques that repair faulty cells by replacing them with spare lines are widely used to improve the manufacturing yield of memory devices such as DRAMs. However, due to constraints like hardware overhead, the number of spare lines available for DRAM repair is limited. Therefore, efficient redundancy analysis (RA) algorithms are required to maximize the repair rate by allocating these scarce resources effectively. Although various RA algorithms have been proposed, most are optimized for simple spare structures, resulting in longer analysis time or lower repair rates when applied to modern DRAMs with complex spare structures. To address this limitation, we propose a novel RA algorithm optimized for these advanced spare structures. The algorithm utilizes an enhanced early termination (ET) technique to rapidly identify valid repair solutions and ensures the successful repair of all repairable memories, even with complex spare structures. Experimental results demonstrate that the proposed algorithm reduces analysis time compared to existing algorithms while ensuring complete repair solutions.