CFET-FP: Complementary FET Standard Cell Synthesis with Optimal Transistor Folding and Placement for Design and Technology Co-optimization

It has been widely accepted that Complementary-FET (CFET) is a promising technology, which stacks P-FET on N-FET or vice versa, to achieve this objective. In comparison with synthesizing the conventional FET based standard cells, two prominent optimization tasks in CFET based multi-row cell synthesis that significantly affect the cell quality, in terms of area and routability, are (1)determining transistor folding shapesand (2)determining placement order of transistors with feasible routability. In this work, we propose an optimal solution to the combined problem of tasks 1 and 2. Precisely, wedevelop a search tree-based area-optimal method of transistor folding and placement, in which we accelerate the cost computation of partial solutions by formulating it into dynamic programming while performing a strict feasibility checking of routability of partial solutions. In the meantime, through experiment with benchmark circuits, it is shown that the CFET cells produced by our cell synthesizer are 6% smaller in size on average even with 28% shorter total metal length and 62% less use of metal2 for in-cell routing over the cells produced by the recent state-of-the-art CFET cell generator. Additionally, we conduct a study on design and technology co-optimization (DTCO) by exploring CFET cell architecture to an open-source 64-bit RISC-V CPU block with 7nm node.