ANP-Flow: A System-Level Simulation and Performance Prediction Toolchain for Asynchronous Neuromorphic Hardware Enabling Co-Exploration
Abstract
Energy-efficient neuromorphic hardware with ultra-low power consumption is increasingly promising for edge-AI applications. Most digital neuromorphic hardware is designed with asynchronous circuits as they naturally match the sparsity and event-driven features of neuromorphic computing. However, designing asynchronous neuromorphic hardware faces challenges including lack of system-level hardware simulators and performance prediction methods, making it difficult for designers to explore the non-numeric architecture design space of asynchronous neuromorphic hardware and find an optimal architecture that meets the demands for various edge computing scenarios. In this paper, we put forward ANP-Flow, a toolchain for asynchronous neuromorphic hardware including system-level simulation, performance prediction, and algorithm-hardware coexploration. The key innovations include: 1) A fully asynchronous, highly concurrent system-level simulator is developed for the first time, enabling fast simulations for asynchronous neuromorphic hardware. 2) A novel graph neural network-based hardware latency prediction model and a residual network-based power consumption prediction model are presented for asynchronous neuromorphic hardware. Experimental results show that they respectively achieve over 0.9 of average R-square score and less than 2% of mean average percentage error rate on datasets with various network scales, traffic patterns and process nodes. 3) An algorithm-hardware co-exploration framework is proposed, improving energy-delay product of asynchronous neuromorphic hardware design by 1.8 times compared with the state-of-the-art work. To the best of our knowledge, ANP-Flow is the first end-to-end asynchronous neuromorphic toolchain with an integrated framework from circuit to algorithm, enabling joint algorithm-hardware design space co-exploration.
Fields of Study & Subjects
Advanced Memory and Neural Computing
Ferroelectric and Negative Capacitance Devices
Parallel Computing and Optimization Techniques
Publication details
- Journal / source
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Volume
- 45
- Issue
- 10
- Pages
- 1–1
- Publication date
- 1 January 2026