A High-Density RRAM Memory Architecture With IO-Assisted-Core-Transistor 1T1R Array and Two-Level Encoding for Edge AI Models

The deployment of AI on edge devices requires high-capacity on-chip memory to mitigate the performance and energy overhead of frequent off-chip data movement. Resistive random access memory (RRAM) has emerged as a promising candidate owing to its non-volatility, high storage density, and low read cost. However, its adoption faces several challenges, including reliability concerns at high density, insufficient scalability for increasingly large AI models, and lower access frequency compared to CMOS-based units. In this work, we present a high-density and reliable RRAM memory architecture enabled by algorithm–hardware co-design. On the hardware side, a 1T1R array leveraging small core-voltage transistors for density and peripheral IO transistors for program reliability is introduced, together with a 16-step tunable current source for robust readout. On the algorithm side, a two-level encoding scheme is proposed to compress AI model storage with low implementation cost, while a burst-mode read strategy alleviates the frequency disparity with CMOS processors. Our experiments show a storage density of 17.4Mb/mm2@28nm, with 1.23× to 4.15× compression rate, 4.99× read-out energy reduction compared to SRAM baseline, and 4× higher read frequency. System-level evaluation further confirms the performance and efficiency improvements of the proposed design.