Study on 3-D 1T1R Resistive Random Access Memory and Stacked Array for Chiplet Integration by Parallel Electrothermal Field-Circuit Co-Simulation
Fields of Study & Subjects
Advanced Memory and Neural Computing
VLSI and Analog Circuit Testing
3D IC and TSV technologies
Publication details
- Journal / source
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Volume
- 45
- Issue
- 10
- Pages
- 4863–4875
- Publication date
- 6 February 2026