SpikeLet: Empowering Multichiplet Neuromorphic System With Hierarchical Interconnect and Spatial–Temporal Parallelism

As Spiking Neural Networks (SNNs) scale, their neuron counts exceed the capacity of a single chip, necessitating multi-chip integration. Multi-chiplet systems provide dense, high-bandwidth interconnects but suffer from inefficient inter-chip spike transmission, limited parallelism, and the lack of transmission-aware mapping. We present SpikeLet, the first multi-chiplet neuromorphic system tailored for large-scale SNNs. SpikeLet employs a hierarchical transmission interconnect with an extend-AER protocol to aggregate spikes and decouple intra- and inter-chiplet communication, an event-driven spatial–temporal parallel dataflow that enables cross-layer and cross-timestep parallelism, and a communication-aware hierarchical mapping based on cooperative co-evolution to balance computation and communication across chiplets and cores. On a 4×4-chiplet prototype, SpikeLet reduces transmission latency by 74.2%, improves throughput by 36.6×, and boosts energy efficiency by 39.2× over a 2D multi-chip baseline, demonstrating a compact and scalable platform for next-generation neuromorphic computing.