Modeling Energy and Delay for ECC-Enabled Cache Architectures

With increasing integration density, modern Systems-on-Chips (SoCs), especially on-chip caches and memories, are critically vulnerable to soft errors. Error Correcting Codes (ECC) are the most widely adopted mitigation technique in safety-critical SoCs, making accurate modeling of ECC overheads essential for effective design decisions. Existing cache modeling frameworks such as CACTI consider only the memory overheads for storing ECC check-bits, and neglect the delay and energy costs of ECC combinational logic, assuming them negligible. We extend CACTI to include the delay and energy overheads due to the ECC logic along with the memory-induced ECC overheads. In addition to the configurations supported by CACTI, we model High Reliability (HR) and High Performance (HP) modes of ECC operation for flexible design exploration. Extensive evaluation across SPEC CPU 2006 and MiBench workloads demonstrates the effectiveness of our modeling, highlighting that neglecting logic overheads underestimates the ECC performance and energy overheads by 12% and 18%, respectively, for SPEC CPU 2006, and 12% and 17%, respectively, for MiBench.