Programmable Clocking Scheme in Field-Coupled Nanocomputing

Field-Coupled Nanocomputing (FCN) is a promising paradigm for digital logic computing, where clocking systems form the foundation of circuit logic implementation. Previous FCN clocking schemes suffer from inflexible information flow topology among clock zones due to fixed clock distributions, leading to routing inefficiencies and high hardware overhead. In this paper, a programmable clocking scheme (PCS) is proposed, which, through the design of clock zones and clock generation circuits, enables programmability in the topology of information flow. Additionally, a mathematical encoding method based on bilinear interpolation kernels is introduced to model clock distribution. PCS enables the customization of clocking schemes to meet specific circuit requirements. A full adder and a D flip-flop serve as case studies to validate the universality and effectiveness of PCS. Compared with previous clocking schemes, experimental results demonstrate significant improvements in the full adder: a 1.39% to 79.89% reduction in cell count, 18.75% to 83.95% in area, 40.00% to 83.33% in delay, 72.00% to 99.57% in cost, and 10.84% to 68.79% in power consumption. Similarly, the D flip-flop exhibits a 36.46% to 52.34% reduction in cell count, 30.77% to 67.86% in area, 40.00% to 76.92% in delay, 77.27% to 98.31% in cost, and 46.48% to 62.47% in power consumption. These results confirm that PCS is more suitable for FCN circuit design.