A Novel Grid-Based, Reconfigurable Strong PUF Architecture Integrated With MRAM, Resilient to Learning-Based Inference

This paper presents a reconfigurable physical unclonable function (PUF) architecture integrated into a novel magnetoresistive random-access memory (MRAM) structure to mitigate read disturbance. Designed using 7nm FinFET technology, the design utilizes an advanced writing scheme that enhances area and delay efficiency compared to conventional memory. A resilient writing circuit enables dynamic reconfigurability by altering magnetic tunnel junction (MTJ) states. A novel level converter reduces the transistor count from 14 to 8 without utilizing thick oxide devices, thereby maintaining gate voltages within VDD limits. Post-layout simulations validate the design's efficiency in both memory writing and PUF operation. The PUF array occupies 34.7 μm² and achieves ultra-low energy consumption of 7.78 fJ per bit, making it suitable for IoT applications. Extensive Monte Carlo simulations confirm robust performance, with a worst-case average Bit Error Rate (BER) of 1.89%, an Intra-Hamming Distance (Intra-HD) mean of 0.0077 and a standard deviation (σ) of 0.0027, and excellent uniqueness with an Inter-HD mean of 0.5000 and a σ of 0.016. The PUF exhibits high diffuseness (mean: 0.499, σ: 0.015), passes all NIST randomness tests, and shows strong resistance against learning-based attacks, including Logistic Regression, SVM, MLP, Larq, CNNs, DNNs, and Reinforcement Learning, achieving almost 50% prediction accuracy after training on one million challenge-response pairs. The architecture offers a larger CRP space than the median of benchmarked designs. Evaluated under process, voltage, and temperature (PVT) variations and process corners, the design demonstrates strong reliability, security, and efficiency, featuring a complete system-level architecture for secure authentication, reconfiguration, and enrollment suitable for IoT and edge-security applications.