3D NMC-HBM: Design of 3D Near Memory Computing Architecture in High Bandwidth Memory considering Signal/Power Integrity and Computing Performance

In this paper, we propose a design framework for a 3D near-memory computing architecture in high bandwidth memory (3D NMC-HBM) considering signal/power integrity (SI/PI) and computing performance. The design framework enables the physical co-design of the 3D interconnect and power distribution network (PDN) based on an electrical performance evaluation, while integrating the extracted interconnect-level parameters into a cycle-accurate simulator for a system-level performance evaluation. Each component of the 3D NMC-HBM architecture including the NMC processor die, interconnect channels, and a hierarchical 3D PDN is modeled considering the physical dimensions of the conventional graphics processing unit (GPU)-HBM module. The electrical performance of the 3D NMC-HBM architecture is analyzed using a detailed methodology considering SI for providing the extended bandwidth, and PI to ensure stable power delivery for high performance operation of the NMC processing units. Furthermore, the efficacy of the proposed framework is verified through a system-level evaluation. Integrated with a cycle-accurate GPU simulator, the computing performance and power consumption of the 3D NMC-HBM architecture is evaluated, considering the effects of reduced interconnect length, bandwidth extension, and higher core utilization. The results show that the 3D NMC-HBM architecture achieves higher computing performance and lower power consumption when computing memory-bound workloads, compared to the GPU-HBM.