TopoSizing: An LLM-aided Framework of Topology-based Understanding and Sizing for AMS Circuits

Analog and mixed-signal (AMS) circuit design remains challenging due to the shortage of high-quality data and the difficulty of embedding domain knowledge into automated flows. Traditional black-box optimization achieves sampling efficiency but lacks circuit understanding, which often causes evaluations to be wasted in low-value regions of the design space. In contrast, learning-based methods embed structural knowledge but are case-specific and costly to retrain. Recent attempts with large language models (LLMs) show potential, yet they often rely on manual intervention, limiting generality and transparency. We propose TopoSizing, an end-to-end framework that performs robust circuit understanding directly from raw netlists and translates this knowledge into optimization gains. Our approach first applies graph algorithms to organize circuits into a hierarchical device–module–stage representation. LLM agents then execute an iterative hypothesis–verification–refinement loop with built-in consistency checks, producing explicit annotations. Verified insights are integrated into Bayesian optimization (BO) through LLM-guided initial sampling and stagnation-triggered trust-region updates, improving efficiency while preserving feasibility. On four real-world AMS circuits (OTA, FC-OTA, SACMP, LDO) in a 55-nm CMOS process, TopoSizing achieves 100% correctness in circuit understanding and parameter assignment. In constraint-satisfaction tasks, it delivers 1.4×–4.8× higher sample efficiency and 1.2×–3.5× faster runtime compared with strong baselines, while requiring 2–4× fewer LLM calls than prior LLM-based frameworks. Ablation studies confirm that reliable circuit understanding is essential for these gains.