Calibration and Enhancement of Analytical IR-Drop Model for Resistive Crossbar Arrays

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Authors: Tommaso Rizzi, Alessandro Lambertini, Tommaso Zanotti, Nicola Lepri, Paolo Pavan, Francesco Maria Puglisi, Daniele Ielmini, Cristian Zambelli
Cited by: 1

Abstract

Resistive In-Memory Computing (IMC) architectures emerged as a promising solution for efficiently accelerating Neural Network (NN) workloads on-chip, particularly in edge Artificial Intelligence (AI) applications where energy and area constraints are critical. Among the various challenges limiting IMC adoption, voltage drops caused by parasitic resistances significantly degrade the computational accuracy. While high-fidelity nodal analyses can model these effects accurately, their computational cost makes them unsuitable for system-level AI accelerators design. Analytical models offer a compelling alternative thanks to their speed and simplicity. However, the absence of a systematic method to fit them to different resistive memory devices and crossbar configurations might limit their applicability. In this work, we overcome this limitation by introducing a calibration procedure across a variety of input patterns and weight matrices. Furthermore, we evaluate the models under non-linear I–V characteristics of Resistive Random Access Memory (RRAM) devices fabricated at IHP Microelectronics. Finally, we propose an enhanced analytical model for the better estimation of the voltage drops across the memory cells. Our modeling strategy is benchmarked against state-of-the-art approaches, achieving best-in-class performance among the analytical models in terms of accuracy and runtime. With more than two orders of magnitude improvement in simulation speed and a 5.9% median misalignment in the output currents approximation compared to SPICE-based nodal analysis, the presented solution is a compelling approach for evaluating large-scale IMC systems.

Fields of Study & Subjects

Advanced Semiconductor Detectors and Materials Silicon and Solar Cell Technologies 3D IC and TSV technologies

Publication details

Journal / source
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Pages
1–1
Publication date
1 January 2026