Strategies to Improve Efficiency of Select-Gate Voltage Floating During GIDL-Assisted Erase in 3-D NAND Flash Memory

This study addresses the issue in 3-D NAND flash memory where, during GIDL (Gate-Induced Drain Leakage)-assisted erase, the floating (FT) select-gate cell (SG) approach induces uncertainty in SG voltage (VSG) rise due to the parasitic capacitive suppression (PCS), degrading SG reliability. First, Technology Computer-Aided Design (TCAD) simulations were performed to elucidate the mechanism ofVSGrise in the FT approach (VSG,FT), and a physics-based compact model capable of quantitatively predictingVSG,FTvariations was developed. Strategies to mitigate the degradation ofVSG,FTrise were proposed, ultimately achieving both SG reliability and GIDL erase efficiency while offering a scalable approach. The validity of the proposed strategies was confirmed through a Simulation Program with Integrated Circuit Emphasis (SPICE)-based Monte Carlo simulations using the developed compact model, evaluated from the perspective of threshold voltage distribution.