A Transistor Operating State Constraints-Based Multi-Objective Evolutionary Algorithm for Optimizing Analog Circuit Sizing

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Authors: Chunliang Zhao, Zihui Han, Dunwei Gong, Biao Xu, Mingcheng Zuo, Shujing Gao
Cited by: 1

Abstract

Analog circuit optimization problem is a multi-objective optimization problem involving multiple conflicting performance metrics. Existing methods face challenges of low efficiency due to frequent SPICE simulation calls and generating infeasible solutions caused by physical constraint violations. To address these issues, this paper proposes a conditional cascade network-based analog circuit optimization algorithm (CCN-ACOA). The core innovations of this algorithm include: (1) proposing a Conditional Cascade Network (CCN) as a surrogate model that adopts a ”classify-first, predict-later” strategy, incorporating transistor operating states as hard constraints to ensure design feasibility; (2) designing an information entropy-based model updating strategy that efficiently trains the CCN by performing fine-tuning through incremental data selection and parameter freezing mechanisms; (3) a population correction-based multi-objective optimization method is proposed, which combines a Pareto-based filling criterion with prediction uncertainty and population crowding information to guide the evolutionary direction of the population. Experimental validation on the AI-Circuit dataset and four typical analog circuits demonstrate that the proposed CCN-ACOA outperforms five state-of-the-art analog circuit optimization algorithms in terms of both simulation performance metrics and hypervolume indicators. These results validate that CCN-ACOA provides an effective solution for the automation of analog integrated circuit design.

Fields of Study & Subjects

Evolutionary Algorithms and Applications VLSI and FPGA Design Techniques Advanced Multi-Objective Optimization Algorithms

Publication details

Journal / source
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Pages
1–1
Publication date
1 January 2026