A 40-nm Sub-mJ/Transfer HDC-SNN Hybrid Processor Enabling On-Chip Few-Shot Transfer Learning for IoT Applications

This work presents a brain-inspired processor that combines Hyperdimensional Computing (HDC) and Spiking Neural Network (SNN), or HDC-SNN hybrid, to enable on-chip few-shot transfer learning (FSTL) for IoT applications. Such an HDC-SNN hybrid architecture utilizes SNN for efficient feature extraction to suppress the size of the vector dimension, thus mitigating intensive operations and the memory footprint for HDC. It also leverages the few-shot and single-pass learning capability of HDC, eliminating the need for abundant labeled samples and training epochs. This processor utilizes a task-agnostic spiking HDC encoder to generate spatio-temporal feature vectors, followed by an on-chip learning HDC classifier. Furthermore, the implementation of on-chip learning uses the schemes of weight access from destination-neuron with memory bank (WAD-MB) and batch-by-batch gradient computation (BGC), achieving a significant improvement on training latency and cache size. This design is fabricated in a 40-nm CMOS technology with a peak efficiency of sub-mJ/transfer (mJ/class and mJ/patient by on chip FSTL) at 0.72V and 65MHz, occupying a core area of 1.56 mm2. For typical neuromorphic datasets, this processor achieves a 1.6-35× improvement in training energy per class and a 3.5- 52× reduction in training latency per sample, compared to state-of-the-art processors. For patient-specific and class-incremental scenarios, it achieves an accuracy of over 96% in both ECG arrhythmia detection and bearing anomaly detection. Specifically, it requires only 2-minute training samples for a new patient with 0.1 mJ energy, achieving a 4.5× improvement in energy efficiency; it employs 3-shot learning for a new class with only 0.3 mJ energy, reducing training epochs by over 100×.