RARPIM: A Robust and Adaptive 1FeFET-1T-1C Based Compute-in-Memory Macro With Capacitor Reused Pipeline SAR ADC

Non-volatile memories (NVM) based computing-in-memory (CIM) architectures suffer from device non-uniformity that causes output deviations. Charge-domain computation mitigates this issue by using capacitor-based charge accumulation but increases area overhead. Earlier approaches reuse the computation array capacitors for Analog-to-Digital Conversion (ADC), yet the conventional structure allows less than half of the capacitors to be reused, limiting both utilization efficiency and conversion precision. The reduced ADC resolution further leads to accuracy degradation in practical neural network applications. To address these challenges, we propose a robust and adaptive 1FeFET-1T-1C CIM macro that reuses nearly all array capacitors within a pipeline SAR ADC architecture, achieving high resolution while maintaining compact area efficiency and lowering latency. Moreover, a charge redistribution mechanism enables analogdomain multi-bit accumulation, eliminating the need for external adder trees and shift circuits. In addition, an adaptive row activation scheme dynamically optimizes the number of active rows based on real-time workload demands. Implemented in a SMIC 55nm PDK, the proposed macro achieves a peak energy efficiency of 97.8 TOPS/W and an area efficiency of 1.153 TOPS/mm2. The efficiency is further enhanced under lightweight models, with adaptive row activation achieving up to 51.17% power reduction.