FPGA-Based Hardware Acceleration of Kolmogorov-Arnold Networks for Edge Inference

Kolmogorov-Arnold Networks (KANs) have recently emerged as an alternative to Multi Layer Perceptrons (MLPs), offering enhanced function approximation through learnable basis functions. While KANs have demonstrated competitive performance at lower parameter counts in diverse machine learning tasks, their high computational demands restrict adoption in edge inference scenarios, where devices operate under stringent power, area, and latency constraints. However, custom-built hardware accelerators for KANs that efficiently compute the B-spline basis functions by exploiting their inherent mathematical properties and sparsity emerge as a promising alternative for edge inference. In this work, we propose one such FPGA-based hardware accelerator to specifically target KAN inference, optimized for edge deployment. Our accelerator exploits the above-mentioned properties of the B-spline basis function to optimize the hardware and uses a weight-fetching strategy that only fetches weights corresponding to non-zero basis function values from the DDR memory. The design is fully pipelined, achieving the same throughput as the input data rate, which is further optimized by the sparsity-aware weight fetching strategy. The design is also scalable with high-bandwidth memory interfaces with wider data ports. Implemented on a Zynq 7020 SoC, the accelerator prototype achieves up to 14× and 1100× higher throughput compared to edge GPUs and CPUs, respectively. The complete end-to-end system utilizes less than 15% of the FPGA’s resources while consuming 2.22 W of power. These results demonstrate the viability of FPGA-based KAN acceleration for real-time edge AI inference.