Compact Memristor Emulator with SDDP for Integrated Neuromorphic Temporal Learning

A dynamic-threshold MOSFET (DTMOS) based circuit with a back-gate biasing is introduced as a new memristor emulator. The memristor emulator uses only two MOSFETs and a capacitor, which allows for large-scale integration and high-frequency operation as high as 200 MHz. This memristor emulator can be used in both grounded and floating configurations, which simplifies the circuit structure for monolithic integration. The emulator’s performance, validated through comprehensive parametric evaluations, shows consistent pinched hysteresis loops (PHLs) at various frequencies, process corners and enables neuromorphic system designs capable of training and detection, supporting spike density-dependent plasticity (SDDP). To achieve SDDP, the memristor emulator is integrated with a fundamental switching circuitry. Additionally, pre and post-layout validations are conducted using computer aided design tool (i.e., Cadence Virtuoso) with 180-nm process design kits (PDKs) from the SCL to further demonstrate the circuit’s efficacy in neuromorphic designs. The proposed memristor emulator was implemented and tested on hardware using IC HCF4007UBE, demonstrating its memristive characteristics. The proposed architecture shows promise for low-power and compact design features, occupying an area of 0.569 mm2 and consuming only 1.041 mW of power for a single-column 64-bit crossbar array at an SCL 180 nm technology node.