Analog Neuron to Minimize ADC/DAC Overhead in Edge-Device ANN Training

Efficient on-chip artificial neural network (ANN) training is essential for adaptive and privacy-preserving edge intelligence. In-memory computing (IMC) offers a promising approach to accelerate on-chip training by minimizing the costly data movement between memory and compute units. However, analog IMC-based training is constrained by the interface mismatch between analog compute arrays and digital neuronal processing. Analog-to-digital and digital-to-analog converters (ADCs/DACs), positioned at layer boundaries for interlayer communication, dominate area, energy, and latency, forming a major bottleneck for scalable edge training. To address these challenges, this work introduces an analog neuron capable of performing interlayer computations and retaining intermediate values entirely in the analog domain, thereby substantially reducing the need for conversion during both training and inference. First, we present the analog neuron, designed and fabricated in GF-RFSOI 45nm technology, which exhibits strong robustness to PVT variations in post-layout simulations. This robustness is attributed to a threshold-driven analog design that ensures stable operation across PVT variations. Second, by minimizing converter involvement in neuronal operations, the proposed architecture achieves significant hardware efficiency improvements. It provides over 20× area reduction, 60× energy savings, and approximately ∼ 5× latency improvement for forward and backward propagation compared to conventional IMC-based training schemes. Third, experimental measurements of the fabricated prototype further validate the circuit behaviour, showing close agreement with simulations and a deviation of only ∼ 1.6% in threshold voltage. Finally, system-level evaluations demonstrate that training with measured neuron characteristics maintains convergence and accuracy across multiple network architectures and datasets.