A High-Rate-Compatible Algebraic GC-LDPC Code for 3-D TLC NAND Flash Memory

The escalating storage density of three-dimensional (3D) NAND flash memory introduces heightened channel noise, significantly degrading channel quality and exacerbating the raw bit error rate (RBER). The fixed and unchangeable code rate of the traditional global coupled low-density-parity-check (GC-LDPC) codes fails to address the performance mismatch arising from the stochastic temporal and spatial fluctuations in 3D NAND flash channels. To address the above issue efficiently, in this paper we investigate high-rate-compatible LDPC codes in 3D NAND flash memory. Firstly, we analyze the flash memory channel characteristics from the FPGA test platform and model the 3D triple-level cell (TLC) NAND flash channel. Subsequently, we propose a novel High-Rate-Compatible Algebraic GC-LDPC (HRC-A-GC-LDPC) code and conduct a comprehensive theoretical analysis of its structure and performance. Specifically, the HRC-A-GC-LDPC code features an information bit length of 4 KB and supports dynamic adjustment to multiple code rates, enabling it to match the varying characteristics of 3D NAND flash channels. This paper also examines and analyzes various construction methods for the HRC-A-GC-LDPC code corresponding to different column weights (CWs), providing insights into its design flexibility. Simulation results demonstrate that, in 3D TLC NAND flash memory, the proposed HRC-A-GC-LDPC code outperforms conventional GC-LDPC codes in both error correction capability and extended memory lifetime, validating its suitability for high-density 3D NAND flash applications.