Machine Learning Predictive Modeling and Multiobjective Optimization of 2.3-D Chip-Last Fan-Out Wafer-Level Packages

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Authors: Mohammad Rafiee, Hao Liu, Zhongtian Xia
Cited by: 2
References: 23

Abstract

This paper presents a surrogate-driven, multi-objective co-design methodology combined with multi-criteria decision making for 2.3D Chip-last (RDL Redistribution layer-first) fan-out wafer-level packages (FOWLP). A 500-point finite-element dataset spanning discrete materials and geometries is used to learn Random Forest and XGBoost surrogates for four objectives: junction-to-ambient thermal resistance (ΘJA) and volume-averaged strain-energy density at the flip-chip bump, C4, and BGA (ΔWbump,ΔWc4,ΔWBGA). The surrogates guide NSGA-II exploration; RadViz provides a compact four-objective view; a NetFlow-based decision step selects a balanced design. Feature-importance analyses agree across models and match packaging physics. ΘJA is governed primarily by the mold path—mold thermal conductivity and mold cap thickness—followed by heatsink and TIM resistances; board-downward terms are secondary. Reliability metrics are controlled by levers local to each tier: silicon thickness and underfill CTEs near the die/interposer region, and BGA alloy with board/package CTEs at the board interface. A cooperative trend is observed for die thickness: within the explored range, thinning the die reduces ΔWnear the die side without materially degrading ΘJA in a mold-dominated stack. Pareto sets and their RadViz embeddings reveal broad regions of low ΘJA coexisting with acceptable ΔW, from which a reliability-first champion is selected. The framework yields interpretable trade-offs and accelerates search for manufacturable 2.3D FOWLP configurations while reducing reliance on exhaustive FEA sweeps.

Fields of Study & Subjects

3D IC and TSV technologies Electronic Packaging and Soldering Technologies Silicon Carbide Semiconductor Technologies

Publication details

Journal / source
IEEE Transactions on Components Packaging and Manufacturing Technology
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Volume
16
Issue
8
Pages
1804–1813
Publication date
10 February 2026