Coaxial Gate/Kelvin Interconnects for Reduced Gate Loop Inductance and Common Source Mutual Inductance in Power Semiconductor Packages

A coaxial gate/kelvin interconnect is proposed to limit gate loop inductance in vertical package structures. While low-inductance solutions have been demonstrated for planar packages, existing interconnects for vertical package structures result in high inductance per unit length. The coaxial gate/kelvin interconnect proposed here has been shown to reduce per-unit length gate-loop inductances in vertical package structures by 50% or more, enabling more advanced vertical package structures. The proposed on-chip coaxial interconnect also results in significant decoupling between the gate and power loops, enabling faster switching and better control of parallel die. This paper explores several materials and techniques for implementing coaxial interconnects. The resultant electrical characteristics, bond strengths, and viability of these approaches were evaluated. A solution for limiting mechanical stress in the bond between the die and the coaxial interconnects due to mechanical loading on the unbonded end was developed. To demonstrate the viability of the proposed interconnect solution, a package prototype which includes coaxial gate/kelvin interconnects was fabricated and characterized.