Experimental Study of Process-Induced Warpage and Assembly Risks in Ultra-Large Multi-Chip FCBGA Packages

Ultra-large multi-chip FCBGA packages are increasingly adopted in high-performance computing, yet their assembly is highly susceptible to warpage-induced defects during high-temperature processing. This work experimentally investigates the effects of assembly sequence and process-stage warpage control using a 102 mm × 102 mm four-die FCBGA test vehicle. Two representative assembly routes, flip-chip-first (FCF) and ring-attach-first (RAF), are systematically compared based on full-process warpage measurements. The results reveal distinct warpage evolution paths governed by free versus constrained substrate conditions. In the FCF route, severe solder-on-pad (SOP) region warpage during chip attach and underfill curing enlarges the chip–substrate gap, significantly increasing the risk of solder non-wetting and bridging. A process-level magnetic compensation approach applied during flip-chip bonding effectively suppresses SOP-region warpage, improves bump height uniformity, and enables stable FCF assembly. In contrast, the RAF route suppresses global warpage through early stiffener attachment but remains vulnerable to localized SOP-region deformation and rapid warpage variation at elevated temperatures, leading to bump-related defects at package corners. These results establish a clear process-warpage-risk relationship. Screening-level JEDEC reliability tests show no functional failure or electrical discontinuity, confirming the feasibility and robustness of the proposed assembly strategy.