Machine Learning-Based Co-Design of Advanced Flip-Chip Packages: Co-Optimization of Package Warpage, Die Stress, Solder-Joint Reliability, Thermal Management, and Signal Integrity

Advanced flip-chip packages must satisfy thermal limits, chip–package interaction constraints, solder-joint reliability, and increasingly tight signal-integrity (SI) margins. These requirements are strongly coupled. A design change that improves one metric can degrade another. Prior studies often optimize thermal or thermo-mechanical metrics in isolation, or treat SI separately from package reliability. A unified workflow for concurrent thermal–mechanical–electrical screening at the package-architecture stage is still limited. This paper presents an ML-assisted co-design workflow for advanced flip-chip packages. The framework combines thermo-mechanical FEA, a steady-state thermal model, and full-wave EM analysis. Six objectives are considered jointly: junction-to-ambient thermal resistance (ΘJA), package warpage (Wpkg), maximum principal stress in the ELK/BEOL region (σELK), viscoplastic work-based fatigue indicators for first-level bumps and second-level BGAs (ΔWbump, ΔWBGA), and a differential insertion-loss metric (ILDD21, derived from SDD21). A Latin Hypercube Sampling spans key material, geometry, and thermal-stack parameters. SI is evaluated using discrete, manufacturable substrate-core options anchored by EM simulations. Random Forest and XGBoost surrogates are trained (5-fold cross-validation) for the thermo-mechanical and thermal objectives and embedded in NSGA-II to generate Pareto-optimal trade-offs. The Net Flow Method is then used to rank Pareto candidates and identify a transparent “champion” design, which is re-simulated as a physics-based check. The workflow enables rapid and explainable exploration of coupled trade-offs. It also provides a practical screening method for early-stage flip-chip package architecture selection under mixed thermal, reliability, and SI constraints.