Self-Compensating StrongARM Latch for High-Speed Energy-Efficient True Random Number Generators

This paper presents a self-compensating StrongARM latch topology tailored for high-speed and energy-efficient true random number generator (TRNG) design. Unlike conventional approaches that rely on auxiliary controllers to monitor the output and apply compensation, the proposed latch incorporates a coupling capacitor and internal feedback path, which autonomously mitigate offset voltages induced by transistor mismatch. This inherent self-compensation not only simplifies the overall architecture but also improves robustness against PVT variations. A TRNG prototype is realized by integrating four self-compensating StrongARM latches with a lightweight XOR-based post-processing stage, thereby ensuring high-quality randomness with minimal design complexity. The statistical properties of the generated bitstreams are verified through NIST SP 800-22 and NIST SP 800-90B test suites, confirming compliance with standard randomness and robustness requirements. Post-layout simulations in a 65-nm low-power CMOS process demonstrate that the proposed TRNG achieves a throughput of 2 Gbps while consuming only 0.107 pJ/bit, highlighting its suitability for energy-constrained security applications.