Shallow Neural Network-Based Error Compensation of a Non-Linear SAR ADC Sampling Stage

Non-idealities of the track-and-hold (T&H) circuit in analog-to-digital converters (ADCs) can severely limit the ADC linearity. In practical applications, traditional calibration techniques are ineffective in suppressing these effects due to the multi-dimensional dependency of the non-idealities on e.g., input voltage, frequency and temperature. To address this, we propose a calibration solution that combines circuit knowledge of the error mechanisms with a data-driven approach into a shallow neural network (NN) containing just 5 neurons. Due to the small size of the NN, the output of the network can be interpreted and referred back to the underlying circuit non-idealities improving the predictability and reliability of the model. The effectiveness of the NN-based calibration is verified on silicon measurements of 10 different 12-bit SAR ADC samples manufactured in a 65nm CMOS technology, demonstrating an average improvement up to 6.8dB and 13.3dB on the measured SNDR and SFDR, respectively. To the best of the author’s knowledge, this is the first demonstration of a compact, interpretable NN-based calibration solution tested over amplitude, frequency, and temperature for multiple samples, while maintaining physics-based insight into the correction process.