MGEMMV: A Multimodal LLM Framework for GEMM Verilog Generation From Circuit Diagrams

Recent advancements in multimodal large language models (MLLMs) have boosted hardware design driven by artificial intelligence (AI), yet a critical gap persists in circuit-diagram-to-Verilog (CD2V) generation—essential for translating structural intent into code. For complex, performance-critical modules, current MLLMs struggle to perform CD2V due to the lack of multimodal datasets that capture hierarchical architectures and hardware optimization techniques (HOTs). General matrix multiplication (GEMM), the computational backbone of AI accelerators that dominates workload and power consumption while demanding deep design expertise, serves as an ideal benchmark for validating CD2V solutions. In this work, we propose MGEMMV, an open-source multimodal framework tailored for GEMM CD2V. It constructs a hierarchical dataset covering basic logic and HOT-enhanced GEMM variants, an automated CD2V pair generation workflow, and a standardized evaluation framework. Experiments show our fine-tuned MLLMs achieve 94.6% syntax and 90.8% functionality correctness, 20.8% and 63.9% higher than the strongest baseline. To our knowledge, MGEMMV is the first GEMM-dedicated CD2V framework, filling a key gap in AI-driven hardware design.