A Novel High-Performance SRAM Design Using Adaptive Write-Assist Circuit and Successive Improvement Offset of SA

This article proposes a novel selective write-assist circuit and a Sense Amplifier (SA) with adaptive offset improvement for low-voltage Static Random Access Memory (SRAM) applications. Upon detection of a write failure in a single SRAM cell, the write-assist circuit is turned on separately to save power consumption. By adaptively improving the offset of SA, the bitline discharge time during SRAM read operations is shortened, achieving a high-speed SRAM read operation. The proposed circuit was integrated into a 256kb SRAM test chip and manufactured using a 40nm CMOS process. Measurement results show that under specific conditions, the access time is 523ps, the dynamic power is$25.03\mu $W/MHz at VDD = 1.21V. The SRAM remains functional at 176MHz with a dynamic power of$11.84\mu $W/MHz when VDD is reduced to 0.81V.