A Single-Channel 12-GS/s 40.5-dB SNDR Time-Domain Stochastic Flash ADC

A time-domain stochastic flash ADC was fabricated using a 12-nm FinFET technology. Its analog input in the voltage domain is transformed into time-domain pulses, which are then sent to a time-to-digital converter (TDC) comprising 405 time comparators. To distinguish the signal timing amplitude, the random input-referred offsets of these comparators are utilized. An input distribution network is employed to broaden the input range of the TDC. A code-mapping calibration method is used to improve the conversion linearity and mitigate the effects of variations in process, voltage, and temperature. Operating at a 12-GS/s sampling rate, the ADC chip consumes 110.7 mW from a 0.8 V supply. It occupies an active area of$480\times 125~\mu \text {m}^{2}$. The ADC achieves an SNDR better than 40.5 dB and an SFDR better than 50.7 dB for input frequencies up to 5.8 GHz.