Design of an Aging-Aware Memory With BTI-Mitigated SA and System-Visible Lifetime Management

The deployment of large language models (LLMs) is critically dependent on the key-value (KV) cache. However, the “write-less, read-many” access pattern of the SRAM tier of KV cache in LLMs poses a reliability challenge. Combined with CMOS scaling, it markedly accelerates aging mechanisms like bias temperature instability (BTI). BTI increases the threshold voltage and slows the devices, posing a severe threat to the reliability of the high-speed KV Cache SRAMs. To address this challenge, this paper proposes an architecture that couples in-situ, path-faithful sensing while exposing interfaces and guidance for system-level reliability management. In this paper,First, we propose an aging-enhanced SRAM cell and sensing amplifier (SA) and their configurable circuit topology to support an aging sensing interface.Second, we present a reconfigurable TDC-based in-situ aging detection circuit. It either detects the aging of cells through the aging sensing interface or replaces the aged cells to maintain their original timing performance.Third, we present a lifetime management strategy that uses the aging detection circuit to monitor the aging status of memory, control its operation modes, and alert its end-of-life alarm. A 28-nm 64-Kbit memory circuit has been constructed to validate the optimizations above. Experiment results show that our proposed aging-aware memory achieves a lifetime of 13.1 years, and after 10 years of operation, the presented aging-aware memory can achieve a maximum operating frequency of 1.47 GHz. Compared with state-of-the-art designs, our proposed design achieves a system lifetime improvement of$\gt 3.9\times $, a maximum SA FoM of 29.5, which is about$2\times $that of SOTA SA designs.