A 2.9-Gb/s Spread-Spectrum Clocking Transceiver Utilizing Phase Interpolation for EMI-Suppressed Chip-to-Chip Links

This paper presents a fully integrated 2.9-Gb/s spread-spectrum clocking (SSC) wireline transceiver designed for high-speed chip-to-chip links. The architecture combines a digitally controlled phase interpolator (DCPI) in the transmitter and an analog-controlled phase interpolator (ACPI) in the receiver, leveraging the programmability of digital control and the low-jitter performance of analog control. A 2.9-GHz four-phase phase-locked loop (PLL) provides reference clocks for both SSC generation and clock/data recovery (CDR). In the transmitter, the DCPI synthesizes SSC-modulated clocks and drives the data path, supporting downward triangular modulation depths up to 3 % at a 44.25-kHz modulation frequency. In the receiver, a quarter-rate SSC-compatible CDR with hybrid PI control recovers the SSC clock and data with fine phase alignment and low jitter. Fabricated in a 90-nm CMOS process and occupying a 1.2 mm$\times 1.2$mm die, the proposed transceiver achieves robust electromagnetic-interference (EMI) suppression, with the SSC generator providing up to 26.78 dB EMI attenuation.