Compressive Image Encoder Architecture for In-Sensor Feature-Space Sampling

An architecture for the on-chip implementation of a compressive image encoder is presented. It is 100% compatible with standard CMOS image sensor architectures. It does not interfere with normal CMOS image sensor operation. No significant image degradation is expected. A stream of compressed vectors containing feature-space samples is provided in parallel with the full raw image data. The major technical challenges posed by the additional in-sensor circuitry are: introducing negligible disturbances on image capture and maintaining image resolution and quality. Concerning the compressive sampling measurement strategy, it is generated on-chip, without requiring storage or communication of the measurement matrix. A new pseudo-diagonal random ternary measurement matrix is proposed that generates compressed vectors that require only 6-bit ADC resolution to render accurate classification results. In addition, the proposed architecture is flexible to implement other measurement strategies. The proposed encoder architecture is implemented in a 110nm CMOS image sensor technology.