HLS-Based Algorithm-Hardware Co-Design of MIMO-OFDM Receiver for Tactical Jamming Suppression

This paper presents an HLS-based algorithm-hardware co-design methodology and complete FPGA hardware accelerator for multi-user massive MIMO-OFDM receivers operating in contested tactical environments with jamming suppression capabilities. We develop a systematic bi-directional co-design methodology using high-level synthesis (HLS) where algorithms provide functional verification constraints while hardware synthesis feedback drives algorithmic complexity reduction, enabling efficient transformation from signal processing algorithms to optimized circuit implementations on the Xilinx ZCU111 radio frequency system-on-chip (RFSoC) platform. The primary contributions include: 1) hardware architecture innovations featuring QR decomposition-based synchronization achieving 330 MHz post-route operation and optimized frequency-domain minimum mean square error (FD-MMSE) equalization with systematic loop restructuring for data dependency removal in substitution modules, reducing hardware resources by 56% lookup tables (LUTs), 58% flip-flops (FFs), and 67% digital signal processing (DSP) blocks while maintaining real-time throughput; 2) systematic HLS-based co-design framework enabling automated architecture exploration with hardware-oriented algorithm adaptations including silent-period frame structure and Cholesky-based decision-feedback equalization; 3) complete system integration validated through field trials demonstrating 8 dB jamming suppression improvement with reliable spatial division multiple access (SDMA) communications. The presented methodology provides insights applicable to broader signal processing systems with stringent real-time constraints.